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16 - bit, 20 msps /40 msps /65 msps /80 msps , 1.8 v analog - to - digital converter data sheet ad9266 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may r esult from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features 1.8 v analog supply operation 1.8 v to 3.3 v output supply snr 77.6 dbfs at 9.7 mhz input 71.1 dbfs at 200 mhz input sfdr 93 dbc at 9.7 mhz input 80 dbc at 200 mhz input low power 56 mw at 20 msps 1 13 mw at 80 msps differential input with 700 mhz bandwidth on - chip voltage reference and sample - and - hold circuit 2 v p - p differential analog input dnl = ? 0.6 /+1.1 lsb interl eaved data o utput for reduced pin - count interface serial port control options offset binary, g ray code, or twos complement data format optional clock duty cycle stabilizer integer 1 - to - 8 input clock d ivider built - in selectable digital t est pattern generation energy - saving power - down modes data clock out put (dco) with programmable clock and data alignment applications communications diversity r adio systems multimode digital receivers gsm, edge, w - c d m a, lt e, cdma2000, wimax, td - scdma smar t antenna systems battery - powered instruments handheld scope meters portable medical i maging ultrasound radar/lidar pet/spect imaging functional block dia gram vin+ vin? vref sense or d1_d0 d15_d14 8 dco sdio agnd dr vdd a vdd sclk spi programming d at a vcm rbias pdwn dfs clk+ clk? mode controls dut y cycle st abilizer divide 1 t o 8 mode csb ref select adc core cmos output buffer ad9266 08678-001 figure 1 . product highlights 1. the ad9266 operates from a single 1. 8 v analog power supply and features a separate digital output driver supply to a c commodate 1.8 v to 3.3 v logic families. 2. the patented sample - and - hold circuit maintains excellent perfor m ance for input frequencies up to 200 mhz and is designed for low cost , low power , and ease of use. 3. a standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider , power - down, dco and data output (d15 _d14 to d1_ d0) timing and offset adjustments, and v oltage refe r ence mode s. 4. the ad9266 is packaged in a 32 - lead ro hs - compliant lfcsp that is pin compatible with the ad9609 10- bit adc, the ad9629 12- bit adc , and the ad 9649 14- bit adc , e nabl ing a simple migra tion path between 10 - bit and 16- bi t converters sampling from 20 msps to 80 msp s .
ad9266 data sheet rev. a | page 2 of 32 table of contents featur es ............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product highlight s ........................................................................... 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 dc specifications ......................................................................... 4 ac specifications .......................................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 7 timing specifications .................................................................. 8 absolute maxim um ratings ............................................................ 9 thermal characteristics .............................................................. 9 esd caution .................................................................................. 9 pin configu ration and function descriptions ........................... 10 typical performance characteristics ........................................... 11 ad9266 - 80 .................................................................................. 11 ad9266 - 65 .................................................................................. 13 ad9266 - 40 .................................................................................. 14 ad9266 - 20 .................................................................................. 15 e quivalent circuits ......................................................................... 16 theory of operation ...................................................................... 17 analog input considerations .................................................... 17 voltage reference ....................................................................... 19 clock input considerations ...................................................... 20 power dissipation and standby mode .................................... 22 digital outputs ........................................................................... 22 timing ......................................................................................... 23 output test ...................................................................................... 24 output test modes ..................................................................... 24 serial port interface (spi) .............................................................. 25 configuration using the spi ..................................................... 25 hardware interface ..................................................................... 26 configuration without the spi ................................................ 26 spi accessible features .............................................................. 26 memory map .................................................................................. 27 reading the memory map register table ............................... 27 open locations .......................................................................... 27 default values ............................................................................. 27 memory map register table ..................................................... 28 memory map registe r descriptions ........................................ 30 applications information .............................................................. 31 design guidelines ...................................................................... 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 6/12 rev. 0 to rev. a changes to table 1 ............................................................................. 4 changes to table 4 ............................................................................. 7 changed built - in self - test (bist ) and output test section to output test section ......................................................................... 24 changes to output test section; deleted built - in self - test (bist) section .................................................................................. 24 changes to tabl e 16 ......................................................................... 28 04 /10 revision 0 : initial version
data sheet ad9266 re v. a | page 3 of 32 general description the ad9266 is a monolithic, single - channel 1.8 v supply, 16- bit , 20 msps /40 msps /65 msps /80 msps analog - to - digital converter (adc) . it featur es a high performance sample - and - hold circuit and on - chip voltage reference. the product uses multistage differe n tial pipeline architecture with output error correction logic to provide 16 - bit accuracy at 80 msps data rates and to guarantee no missing codes over the full opera t ing temperature range. the adc contains several features designed to maximize flexibility and minimize system cost, such as programmabl e clock and data alignment and programmable digital test pattern generation. the available digital test patterns include built - in deterministic and pseudorandom patterns, along with custom user - defined test patterns entered via the serial port interface (s pi). a differe n tial clock input w ith a selectable internal 1 - to - 8 divide ratio controls all internal conversion cycles. an optional duty cycle stabilizer (dcs) compensates for wide variations in the clock duty cycle while maintaining excellent overall adc pe r formance. the interleaved digital output data is presented in offset binary, gray code, or twos complement format . a data output clock (dco) is pr o vided to ensure proper latch timing with receiving logic. both 1.8 v and 3.3 v cmos levels are supported . the ad9266 is available in a 32 - lead rohs - compliant lfcsp and is spec i fied over the industrial temperature range (?40c to +85c).
ad9266 data sheet rev. a | page 4 of 32 specifications dc specifications avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v int ernal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. table 1. parameter temp ad9266 - 20/ ad9266 - 40 ad9266 - 65 ad9266 - 80 unit min typ max min typ max min typ max resolution full 1 6 1 6 1 6 bits accuracy no missing codes full gua r anteed guara n teed guara n teed offset error full + 0.05 0.3 0 + 0.05 0.3 0 + 0.05 0.3 0 % fsr gain error 1 full ?2.5/ ?2.0 ?1 .0 + 1 .0 % fsr differential nonlinearity (dnl) 2 full ?0.9/+1.2 ? 0.9/+1. 7 ?0.9 /+1. 7 lsb 25c ?0.5/+0.6 ?0.5/+1. 0 ?0.6 /+1.1 lsb integral nonli n earity (inl) 2 full 5.5 6.5 6.2 lsb 25c 1.8 2. 4 3. 5 lsb temperature drift offset error full 2 2 2 ppm/c internal vol t age reference output voltage (1 v mode) full 0.983 0.995 1.007 0.983 0.995 1.007 0.983 0.995 1.007 v load regul a tion error at 1.0 m a full 2 2 2 mv input - referred noise vref = 1.0 v 25c 2.8 2 .8 2.8 lsb rms analog input input span, vref = 1.0 v full 2 2 2 v p - p input capac i tance 3 ful l 6 .5 6 .5 6 .5 pf input common - mode voltage full 0.9 0.9 0.9 v input common - mode range full 0.5 1.3 0.5 1.3 0.5 1.3 v refere nce input resistance full 7.5 7.5 7.5 k? power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 3.6 1.7 3.6 1.7 3.6 v supply current iavdd 2 full 31.4 / 40.7 33.2 / 42.5 54.5 57.6 62.5 65.7 ma idrvdd 2 (1.8 v) full 1. 7 / 3.3 5.2 6.3 ma idrvdd 2 (3.3 v) full 3.0 / 5.9 9.3 11.6 ma power co n sumption dc input full 57/ 73 98 113 mw sine wave i n put 2 (drvdd = 1.8 v) full 60/ 79 63/ 82 107 113 124 130 mw sine wave i n put 2 (drvdd = 3.3 v) full 66/ 93 129 151 mw standby power 4 full 40 44 44 mw power - down power full 0. 5 0 . 5 0. 5 mw 1 measured with 1.0 v external reference. 2 m easured with a 10 mhz input frequency at rated sample rate, full - scale sine wave, with approximately 5 pf loading on each output bit. 3 input capacitance refers to the effective capacitance between the differential input s . 4 standby power is measured wi th a dc input and the clk active.
data sheet ad9266 re v. a | page 5 of 32 ac specifications avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unle ss ot h erwise noted. table 2. parameter 1 temp ad9266 - 20/ ad9266 - 40 ad9266 - 65 ad9266 - 80 unit min typ max min typ max min typ max signal - to - noise ratio (snr) f in = 9.7 mhz 25c 78.2 77.9 77.6 dbfs f in = 30.5 mh z 25c 77.6 77.5 77.3 dbfs full 76.7 76.6 dbfs f in = 70 mhz 25c 75.8/76.4 76.6 76.6 dbfs full 75.5 dbfs f in = 200 mhz 25c 72.1 dbfs signal - to - noise - and - disto r tion (sinad) f in = 9.7 mhz 25c 78.0 77.7 77.4 dbfs f in = 30.5 mhz 25c 77.5 77.3 77.1 dbfs full 76.2 76.2 dbfs f in = 70 mhz 25c 75.7/76.3 76.5 76.6 dbfs full 75.5 dbfs f in = 200 mhz 25c 69.4 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.7 12.6 12.6 bits f in = 30.5 mhz 25c 12.6 12.5 12.5 bits f in = 70 mhz 25c 12.3/ 12.4 12.4 12.4 bits f in = 200 mhz 25c 11.2 bits worst second or third ha r monic f in = 9.7 mhz 25c ?97 ?96 ?95 dbc f in = 30.5 mhz 25c ?96/?93 ?9 4 ?93 dbc full ?80 ?80 dbc f in = 70 mhz 25c ?97/?95 ?98 ?95 dbc full ?80 dbc f in = 200 mhz 25c ?80 dbc spurious - free dynamic range (sfdr) f in = 9.7 mhz 25c 95 95 94 dbc f in = 30.5 mhz 25c 93 92 92 dbc full 80 80 dbc f in = 70 mhz 25c 93 95 93 dbc full 80 dbc f in = 200 mhz 25c 80 dbc worst other (harmonic or spur) f in = 9.7 mhz 25c ?102 ? 101 ?99 dbc f in = 30.5 mhz 25c ?102 ?10 1 ?9 8 dbc full ?89 ? 89 dbc f in = 70 mhz 25c ?101 ?100 ?98 dbc full ?89 dbc f in = 200 mhz 25c ?86 dbc two - tone sfdr f in = 30. 5 mhz (?7 dbfs), 32.5 mhz (?7 dbfs) 25c 90 90 90 dbc analog input bandwidth 25c 700 700 700 mhz 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions.
ad9266 data sheet rev. a | page 6 of 32 digital specificatio ns avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. table 3. parameter temp ad9266 - 20/ ad9266 - 40/ ad9266 - 65/ ad9266 - 80 unit min typ max differential clock inputs (clk+, clk ? ) logic compliance cmos/lvds/lvpecl internal co m mon - mode bias full 0.9 v differential i n put voltage full 0.2 3.6 v p - p input voltage range full gnd ? 0.3 avdd + 0.2 v high level i n put current full ?10 +10 a low level input current full ?10 +10 a input resistance full 8 10 12 k ? input capac i tance full 4 pf logic i n puts (sclk/d fs, mode, sdio/pdwn ) 1 high level i n put voltage full 1.2 drvdd + 0.3 v low level input voltage full 0 0.8 v high level i n put current full ?50 ? 75 a low level input current full ?10 +10 a input resistance full 30 k ? input capac i tance full 2 pf logic i n puts ( csb ) 2 high level i n put voltage full 1.2 drvdd + 0.3 v low level input voltage full 0 0.8 v high level i n put current full ?10 +10 a low level input current full 40 135 a input resistance full 26 k? input capac i tance full 2 pf digital outputs drvdd = 3.3 v high level output voltage, i oh = 50 a full 3.29 v high level output voltage , i oh = 0.5 ma full 3.25 v lo w level output voltage, i ol = 1.6 ma full 0.2 v low level out put voltage , i ol = 50 a full 0.05 v drvdd = 1.8 v high level output voltage , i oh = 50 a full 1.79 v high level output voltage , i oh = 0.5 ma full 1.75 v low level output vo ltage, i ol = 1.6 ma full 0.2 v low level output voltage , i ol = 50 a full 0.05 v 1 internal 30 k ? pull - down. 2 internal 30 k ? pull - up.
data sheet ad9266 rev. a | page 7 of 32 switching specificat ions avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. table 4. parameter temp ad9266 - 20/ ad9266 - 40 ad9266 - 65 ad9266 - 80 unit min typ max min typ max min typ max clock input param e ters input clock rate full 80/ 320 520 625 mhz conversion rate 1 full 3 20/40 3 65 3 80 msps clk period divide - by - 1 mode (t clk ) full 50/25 15.38 12.5 n s clk pulse width high (t ch ) 25.0/12.5 7.69 6.25 ns aperture delay (t a ) full 1.0 1.0 1.0 ns aperture uncertainty (jitter, t j ) full 0.1 0.1 0.1 ps rms data output param e ters data propagation delay (t pd ) full 1.84 3 3.90 1 .84 3 3.90 1.84 3 3.90 ns dco propagation delay (t dco ) full 1.86 3 4.04 1.86 3 4.04 1.86 3 4.04 ns dco to data skew (t skew ) full ? 0.53 0.1 0.72 ? 0.53 0.1 0.72 ? 0.53 0.1 0.72 ns pipeline delay (latency) full 9 9 9 cycles wake - up time 2 full 350 350 350 s standby full 600/400 300 260 ns out - of - range recovery time full 2 2 2 cycles 1 conversion rate is the clock rate after th e clk d ivider. 2 wake - up time is dependent on the value of the decoupling capacitors. 08678-002 t clk t a t dco t skew t skew t pd v in clk+ clk? dco d1_d0 n ? 1 n n + 1 n + 2 n + 3 n + 5 n + 6 n + 7 n + 8 d1 n?9 d0 n?9 d1 n?8 d0 n?8 d1 n?7 d0 n?7 d1 n?6 d0 n?6 d1 n?5 d0 n?5 d1 n?4 d0 n?4 d15 n?9 d14 n?9 d15 n?8 d14 n?8 d15 n?7 d14 n?7 d15 n?6 d14 n?6 d15 n?5 d14 n?5 d15 n?4 d14 n?4 d15_d14 figure 2 . cmos output data timing
ad9266 data sheet rev. a | page 8 of 32 timing specification s table 5. parameter conditions min ty p max unit spi timing requirements t ds setup time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high sclk pulse width high 10 ns t low sclk pulse width low 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge 10 ns
data sheet ad9266 rev. a | page 9 of 32 absolute maximum rat ings table 6. parameter rating avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ? 0.3 v to +3.9 v vin+, vin? to agnd ? 0.3 v to avdd + 0.2 v clk+, clk? to agnd ? 0.3 v to avdd + 0.2 v vref to agnd ? 0.3 v to avdd + 0.2 v sense to agnd ? 0.3 v to avdd + 0.2 v vcm to agnd ? 0.3 v to avdd + 0.2 v rbias to agnd ? 0.3 v to avdd + 0.2 v csb to agnd ? 0.3 v to drvdd + 0.3 v sclk/dfs to agnd ? 0.3 v to drvdd + 0.3 v sdio/pdwn to agnd ? 0.3 v to drvdd + 0.3 v mode/or to agnd ? 0.3 v to drvdd + 0.3 v d1_d0 t hrough d15_d14 to agnd ? 0.3 v to drvdd + 0.3 v dco to ag nd ? 0.3 v to drvdd + 0.3 v operating temperature range (ambient) ? 40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ? 65c to +150c stresses above those listed under absolute maximum ratings may cause perm anent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditi ons for extended periods may affect device reliability. thermal characterist ics the exposed paddle is the only ground connection for the chip. the exposed paddle must be soldered to the agnd plane of the us ers circuit board. soldering the exposed paddle to the us ers board also increases the reliability of the solder joints and maximizes the thermal capability of the package. table 7 . thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 jt 1, 2 unit 3 2 - lead lfcsp 5 mm 5 mm 0 37.1 3.1 20.7 0.3 c/w 1.0 32.4 0.5 c/w 2.5 29.1 0.8 c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - std 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer pcb with a solid ground plane. as shown in table 7 , airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, throug h holes, ground, and power planes r e duces the ja . esd caution
ad9266 data sheet rev. a | page 10 of 32 pin configuration and function descrip tions notes 1. nc = no connec t . 2. the exposed paddle (pin 0) is the only gnd connection on the chip and must be connected to the pcb agnd. 08678-003 clk+ clk? a vdd csb sclk/dfs sdio/pdwn nc nc a vdd mode/or dco (msb) d15_d14 d13_d12 d1 1_d10 d9_d8 d7_d6 nc nc nc nc dr vdd d1_d0 (lsb) d3_d2 d5_d4 a vdd vin+ vin? a vdd rbias vcm sense vref t op view (not to scale) ad9266 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 32 31 30 29 28 27 26 25 figure 3 . pin configuration table 8. pin function description s pin no. mnemonic descripti on 0 , e xposed paddle agnd the exposed paddle is the only ground connecti on on the chip. it must be soldered to the analog ground of the pcb to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1, 2 clk+, clk? diff erential encode clock for pe cl, lvds, or 1.8 v cmos inputs. 3, 24, 29, 32 avdd 1.8 v supply pin for adc core domain. 4 csb spi chip select. active low enable, 30 k ? internal pull - up. 5 sclk/dfs spi clock input in spi mode (sclk). 30 k ? internal pull - dow n. data format select in non - spi mode (dfs). s tatic control of data output format. 30 k ? internal pull - down. dfs high = twos complement output; dfs low = offset binary output. 6 sdio/pdwn spi data input/output (sdio). bidirectional spi data i/o with 30 k? internal pull - down. non - spi mode power - down (pdwn). static control of chip power - down with 30 k ? internal pull - down. see table 14 for details. 7 to 1 2 nc n o c onnect. 14 to 21 d1_d0 (lsb) to (msb) d15_d14 adc digital outputs . 13 drvdd 1.8 v to 3.3 v supply pin for output driver domain. 22 dco data clock digital output. 23 mode/or chip mode select input (mode)/out - of - range digital output in spi mode (or). default = out - of - range (or) digital output (spi register 0x2a, bit 0 = 1). option = chip mode select input (spi register 0x2a, bit 0 = 0). chip power - down (spi register 0x08, bits[7:5] = 100 b ). chip stand by (spi register 0x08, bits[7:5] = 101 b ). normal operation, output disabled (spi register 0x08, bits[7:5] = 110 b ). normal operation, output enabled (spi register 0x08, bits[7:5] = 111 b ). out - of - range (or) digital output only in non- spi mode. 25 vref 1.0 v voltage reference input/output. see table 10. 26 sense reference mode selection. see table 10. 27 vcm analog output voltage at mid avdd supply. sets common mode of the analog inputs. 28 rbias set analog current bias. connect to 10 k ? (1% tolerance) resistor to ground. 30, 31 vin?, vin+ adc analog inputs.
data sheet ad9266 rev. a | page 11 of 32 typical performance characteristics ad9266 -80 avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. 0 ?140 ?20 ?40 ?60 ?80 ?100 ?120 0 5 10 15 20 25 30 35 40 amplitude (dbfs) frequency (mhz) 80msps 9.7mhz @ ?1dbfs snr = 76.8db (77.8dbfs) sfdr = 94.3dbc 08678-033 figure 4 . ad9266 - 80 single - tone fft with f in = 9.7 mhz 0 ?140 ?20 ?40 ?60 ?80 ?100 ?120 0 5 10 15 20 25 30 35 40 amplitude (dbfs) frequency (mhz) 80msps 69mhz @ ?1dbfs snr = 75.1db (76.1dbfs) sfdr = 89.5dbc 08678-035 figure 5 . ad9266 - 80 single - tone fft with f in = 69 mhz 0 ?15 ?30 ?45 ?60 ?90 ?75 ?105 ?120 ?135 4 8 12 16 20 24 28 32 36 frequency (mhz) amplitude (dbfs) f 2 ? f 1 f 1 + f 2 2 f 1 ? f 2 2 f 2 + f 1 2 f 1 + f 2 2 f 2 ? f 1 80msps 28.3mhz @ ?7dbfs 30.6mhz @ ?7dbfs sfdr = 89.5dbc (96.5dbfs) 08678-053 figure 6 . ad9266 - 80 two - tone fft with f in1 = 28.3 mhz and f in2 = 30.6 mhz 0 ?140 ?20 ?40 ?60 ?80 ?100 ?120 0 5 10 15 20 25 30 35 40 amplitude (dbfs) frequency (mhz) 80msps 30.6mhz @ ?1dbfs snr = 76.5db (77.5dbfs) sfdr = 85.7dbc 08678-034 figure 7 . ad9266 - 80 single - tone fft with f in = 30. 6 mhz 0 ?140 ?20 ?40 ?60 ?80 ?100 ?120 0 5 10 15 20 25 30 35 40 amplitude (dbfs) frequency (mhz) 80msps 210mhz @ ?1dbfs snr = 70db (71dbfs) sfdr = 79.7dbc 08678-036 figure 8 . ad9266 - 80 single - tone fft with f in = 21 0 mhz 10 ?30 ?10 ?50 ?70 ?90 ?110 ?130 ?95 ?65 ?75 ?85 ?55 ?45 ?35 ?25 ?15 input amplitude (dbfs) sfdr/imd3 (dbc/dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 08678-054 figure 9 . two - tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 28.3 mhz and f in2 = 30.6 mhz
ad9266 data sheet rev. a | page 12 of 32 avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ai n = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. 100 90 80 70 60 50 40 30 20 10 0 0 50 100 150 200 input frequency (mhz) snr/sfdr (dbfs/dbc) sfdr (dbc) snr (dbfs) 08678-057 figure 10. ad9266 - 80 snr/sfdr vs. input frequency (ain) with 2 v p - p full scale 100 90 80 70 30 40 50 60 20 10 0 10 20 30 40 50 60 70 80 sample rate (msps) snr/sfdr (dbfs/dbc) sfdr (dbc) snr (dbfs) 08678-055 figure 11 . ad9266 - 80 snr/sfdr vs. sample ra te with ain = 9.7 mhz 120 0 20 40 60 80 100 ?65 ?60 0 ?10 ?20 ?30 ?40 ?50 input amplitude (dbfs) snr/sfdr (dbfs/dbc) snr snrfs sfdr sfdrfs 08678-061 figure 12 . ad9266 - 80 snr/sfdr vs. input amplitude (ain) with f in = 9.7 mhz 1.5 1.0 0.5 ?0.5 0 ?1.0 ?1.5 0 16,384 32,768 49,152 65,536 output code dnl error (lsb) 08678-038 figure 13 . dnl error with f in = 9.7 mhz 0 6 4 2 ?2 ?4 ?6 0 16,384 32,768 49,152 65,536 output code inl error (lsb) 08678-037 figure 14 . inl with f in = 9.7 mh z 4.0m 0 500k 1.0m 1.5m 2.0m 2.5m 3.0m 3.5m number of hits output code n + 10 n + 9 n + 8 n + 7 n + 6 n + 5 n + 4 n + 3 n + 2 n + 1 n n ? 1 n ? 2 n ? 3 n ? 4 n ? 5 n ? 6 n ? 7 n ? 8 n ? 9 n ? 10 n ? 11 n ? 12 2.8 lsb rms 08678-048 figure 15 . grounded input histogram
data sheet ad9266 rev. a | page 13 of 32 ad9266 -65 avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input , 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 65msps 9.7mhz @ ?1dbfs snr = 76.9db (77.9dbfs) sfdr = 95.9dbc 08678-030 figure 16 . ad9266 - 65 single - tone fft with f in = 9.7 mhz 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 65msps 69mhz @ ?1dbfs snr = 75.5db (76.5dbfs) sfdr = 87.4dbc 08678-032 figure 17 . ad9266 - 65 single - tone fft with f in = 69 mhz 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 30 25 20 15 10 5 amplitude (dbfs) frequency (mhz) 65msps 30.6mhz @ ?1dbfs snr = 76.6db (77.6dbfs) sfdr = 89.9dbc 08678-031 figure 18 . ad9266 - 65 single - tone fft with f in = 30.6 mhz 120 0 20 40 60 80 100 ?65 ?60 0 ?10 ?20 ?30 ?40 ?50 input amplitude (dbfs) snr/sfdr (dbfs/dbc) snr snrfs sfdr sfdrfs 08678-060 figure 19 . ad9266 - 65 snr/sfdr vs. input amplitude (ain) with f in = 9.7 mhz 100 90 80 70 60 50 40 30 20 10 0 0 50 100 150 200 input frequency (mhz) snr/sfdr (dbfs/dbc) sfdr (dbc) snr (dbfs) 08678-056 figure 20 . ad9266 - 6 5 snr/sfdr vs. input frequenc y (ain) with 2 v p - p full scale
ad9266 data sheet rev. a | page 14 of 32 ad9266 -40 avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs disabled, unless ot h erwise noted. 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 2 4 6 8 10 12 14 16 18 20 amplitude (dbfs) frequency (mhz) 40msps 9.7mhz @ ?1dbfs snr = 76.9db (77.9dbfs) sfdr = 95.1dbc 08678-028 figure 21 . ad9266 - 40 single - tone fft with f in = 9.7 mhz 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 2 4 6 8 10 12 14 16 18 20 amplitude (dbfs) frequency (mhz) 40msps 30.6mhz @ ?1dbfs snr = 76.6db (77.6dbfs) sfdr = 88.8dbc 08678-029 figure 22 . ad9266 - 40 single - tone fft with f in = 30.6 mhz 120 0 20 40 60 80 100 ?65 ?60 0 ?10 ?20 ?30 ?40 ?50 input amplitude (dbfs) snr/sfdr (dbfs/dbc) snr snrfs sfdr sfdrfs 08678-059 figure 23 . ad9266 - 40 snr/sfdr vs. input amplitude (ain) with f in = 9.7 mhz
data sheet ad9266 rev. a | page 15 of 32 ad9266 -20 avdd = 1.8 v; drvdd = 1.8 v, maximum sample rate, 2 v p - p differential input, 1.0 v internal reference; ain = ?1.0 dbfs, 50% duty cycle clock, dcs dis abled, unless ot h erwise noted. 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1 2 3 4 5 6 7 8 9 10 amplitude (dbfs) frequency (mhz) 20msps 9.7mhz @ ?1dbfs snr = 76.9db (77.9dbfs) sfdr = 95.6dbc 08678-024 figure 24 . ad9266 - 20 single - tone fft with f in = 9.7 mhz 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1 2 3 4 5 6 7 8 9 10 amplitude (dbfs) frequency (mhz) 20msps 30.6mhz @ ?1dbfs snr = 76.7db (77.7dbfs) sfdr = 90.7dbc 08678-026 figure 2 5 . ad9266 - 20 single - tone fft with f in = 30.6 mhz 120 100 80 60 40 20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 input amplitude (dbfs) snr/sfdr (dbfs/dbc) sfdrfs snrfs sfdr (dbc) snr (dbc) 08678-058 figure 26 . ad9266 - 20 snr /sfdr vs. input amplitude (ain) with f in = 9.7 mhz
ad9266 data sheet rev. a | page 16 of 32 equivalent circuits a vdd vin 08678-039 figure 27 . equivalent analog input circuit 7.5k? vref 375? a vdd 08678-047 figure 28 . equivalent vref circuit sense 375? a vdd 08678-046 figure 29 . equi valent sense circuit clk+ clk? 0.9v 15k? 5? 5? 15k? a vdd a vdd 08678-040 figure 30 . equivalent clock input circuit dr vdd d1_d0 t o d15_d14, or 08678-042 figure 31 . equivalent d1_ d0 to d 15_d14 and or digital output circuit 350? dr vdd 30k? sclk/dfs, mode, sdio/pdwn 08678-043 figure 32 . equivalent sclk/dfs, m ode , and sdio/pdwn input circuit 30k? csb 350? a vdd dr vdd 08678-045 figure 33 . equivalent csb input circuit rbias and vcm 375? a vdd 08678-044 figure 34 . equivalent rbias and vcm circuit
data sheet ad9266 rev. a | page 17 of 32 theory of operation the ad9266 architecture consists of a multi stage , pipel ined adc . each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 16- bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample , whereas the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a s witched - capacitor dac and an interstage residue amplifier (for example, a multiplying digital - to - analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pip eline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the cmos output buffers. t he output buffers are powered from a separate (drvdd) supply, allowing adjust - ment of the output voltage swing. during power - down, the outp ut buffers go into a high imped ance state. analog input conside rations the analog input to the ad9266 is a differenti al switched - capacitor circuit designed for processing differential input signals. this circuit can support a wide common - mode range while maintaining excellent performance. by using an input common - mode voltage of midsupply, users can minimize signal - depen dent e r rors and achieve optimum performance. s s h c par c sample c sample c par v i n? h s s h v i n+ h 08678-006 figure 35 . switched - capacitor input circuit the clock signal alternately switches the input circuit between sa m ple - and - hold mode (see figure 35 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected fro m the output stage of the d riving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differ - ential capacitance at the analog inputs and , therefore , achieve the ma ximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a shunt capacitor or two single - ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the i n put to limit unwanted broadband noise. see the an - 742 application note, the an - 827 application note , and the analog dialogue article tr ansformer - coupled front - end for wideband a/d converters (volume 39, april 2005) for more information . in general, the precise values depend on the appl i cation. input common mode the analog inputs of the ad9266 are not internally dc - biased. therefore, in ac - coupled applications, the user must provide a dc bias exte r nally. setting the device so that vcm = avdd /2 is recommended for optimum performance, but the device can function over a wider range with reaso n able performance, as shown in figure 36. 100 95 90 85 80 75 70 65 60 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 snr/sfdr (dbfs/dbc) input common-mode voltage (v) sfdr (dbc) snr (dbfs) 08678-049 figure 36 . snr/sfdr vs. input common - mode voltage, f in = 32.5 mhz, f s = 80 msps an on - board, common - mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be de coupled to ground by a 0.1 f capacitor, as described in the applications information section. differential input configurations optimum performance is achieved while driving the ad9266 in a differential input configuration. for b aseband applications, the ad8138 , ada4937 - 2 , and ada4938 - 2 differential drivers provide excellent performance and a flexible interface to the adc. the output co m mon - mode voltage of the ada4938 - 2 is easily set with the vcm pin of the ad9266 (see figure 37 ), and the driver can be configured in a salle n - key filter topology to provide band limi t ing of the input signal. avdd vin 76.8? 120? 0.1f 33? 33? 10pf 200? 200? 90? ada4938-2 adc vin? vin+ vcm 08678-007 figure 37 . differential input configuration using the ada4938 - 2
ad9266 data sheet rev. a | page 18 of 32 for baseband applications below ~10 mhz where snr is a key para meter, differential transformer c oupling is the reco mmended input config u ration. an example is shown in figure 38 . to bias the analog input, the vcm voltage can be connected to the center tap of the seco n dary winding of the transformer. 2v p-p 49.9? 0.1f r r c adc vcm vin+ vin? 08678-008 figure 38 . differential transformer - coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies b e low a few megahertz (mhz). excessive signal power can also cause core s aturation, which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad9266 . for applications above ~10 mhz where snr is a key p arameter, differential double balun coupling is the recommended input config u ration (see figure 40 ). an alternative to using a transformer - coupled input at frequencies in the second nyquist zone is to use the ad8352 differe n tial driver. an example is shown in figure 41 . see the ad8352 data sheet for more information. in any configuration, the value of shunt capaci tor c is dependent on the input frequency and source impedance and may need to be reduced or removed. tabl e 9 displays the suggested values to set the rc network. however, these values are dependent on the input signal and should be used only as a star t ing guide. table 9 . example rc network frequency range (mhz) r series (? each) c differential (pf) 0 to 70 33 22 70 to 200 125 open single - ended input configuration a single - ended input can provide adequa te performance in cost - sensitive applications. in this configuration, sfdr and distortion performance degrade due to the large input common - mode swing. if the source i m pedances on each input are matched, there should be little effect on snr performance. figure 39 shows a typical single - ended input configuration. 1v p - p r r c 49. 9? 0.1 f 10 f 10 f 0.1 f a v d d 1 k? 1 k? 1 k? 1 k? a d c a v d d vin+ vin? 08678-009 figure 39 . single - ended input configuration adc r 0.1f 0.1f 2v p-p vcm c r 0.1f s 0.1f 25? 25? s p a p vin+ vin? 08678-010 figure 40 . differential double balun input configuration ad8352 0? 0? c d r d r g 0.1f 0.1f 0.1f 0.1f 16 1 2 3 4 5 11 0.1f 0.1f 10 14 0.1f 8, 13 v cc 200? 200? analog input analog input r r c adc vcm vin+ vin? 08678-011 figure 41 . differential input configuration using the ad8352
data sheet ad9266 rev. a | page 19 of 32 voltage reference a stable and accurate 1.0 v voltage reference is built into the ad9266 . the vref can be configured using either the internal 1.0 v reference or an externally app lied 1.0 v reference voltage. the various re f erence modes are summarized in the sections that follow. the reference decoupling section describes the best practices for pcb layout of vref . internal reference connection a compara tor within the ad9266 detects the potential at the sense pin and co nfigures the reference into two possible modes, which are summarized in table 10 . if sense is grounded, the reference amplifier switch is connected to the inter nal resistor divider (see figure 42 ), setting vref to 1.0 v. vref sense 0.5v adc select logic 0.1f 1.0f vin? vin+ adc core 08678-012 figure 42 . internal reference configuration if the internal reference of the ad9266 is used to drive multiple converters to improve gain ma tching, the loading of the reference by the other converters must be considered. figure 43 shows how the internal reference voltage is affected by loa d ing. 0 ?3.0 0 2.0 load current (ma) reference voltage error (%) ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.8 1.2 internal v ref = 0.995v 08678-014 figure 43 . v ref accuracy vs. load current ext ernal reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac - teristics. figure 44 shows the typical drift characteri s tics of the internal refer ence in 1.0 v mode. 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?6 ?40 ?20 0 20 40 60 80 temperature (c) v ref error (mv) v ref error (mv) 08678-052 figure 44 . typical v ref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with a n equivalent 7.5 k? load (see figure 28 ). the internal buffer generates the posi - tive and n egative full - scale references for the adc core. therefor e, the external reference must be limited to a maximum of 1.0 v. table 10 . reference configuration summary selected mode sense vol t age (v) resulting vref (v) resulting differe n tial span (v p - p) fixed internal refe r ence agnd to 0.2 1.0 internal 2.0 fixed external re f erence avdd 1.0 applied to external vref pin 2.0
ad9266 data sheet rev. a | page 20 of 32 clock input considerations for optimum performance, clock the ad9266 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac - coupled into the clk+ and clk ? pins via a transformer or capacitors. these pins are biased internally (see figure 45 ) and require no exte r nal bias. 0.9v avdd 2pf 2pf clk? clk+ 08678-016 figure 45 . equivalent clock input circuit clock input options th e ad9266 has a very f lexible clock input structure. the c lock in put can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used , clock source j itter is of great concern, as described in the jitter considerations section. figure 46 and figure 47 show two preferred methods for clock - ing the ad9266 (at clock rates u p to 625 mhz when using the internal clock divider ). a low jitter cloc k source is converted from a single - ended signal to a di f ferential signal using either an rf transformer or an rf balun. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 08678-017 figure 46 . transformer - coupled differ ential clock (up to 200 mhz) 0.1f 0.1f 1nf clock input 1nf 50? clk? clk+ schottky diodes: hsms2822 adc 08678-018 figure 47 . balun - coupled differential clock (up to 625 mhz) the rf balun configuration is recommended for clock frequencies between 125 mhz and 625 mhz, and the rf transformer is recom - mended for clo ck frequencies from 10 mhz to 200 mhz. the back - to - back schottky diodes across the transformer/ balun secondary limit clock excursions into the ad9266 to approximately 0.8 v p - p differe n tial. this limit helps prevent the large voltage swings of the cloc k from feeding through to other portions of the ad9266 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 48 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter perfor m ance. 10 0? 0.1f 0.1f 0.1f 0.1f 240? 240? 50k? 50k? clk? clk+ clock input clock input adc ad951x pecl driver 08678-019 figure 48 . differential pecl sample clock (up to 625 mhz) a third option is to ac couple a differential lvds signal to the sa m ple clock input pins, as shown in figure 49 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 / ad9516 / ad9517 clock drivers offer excellent jitter perfor m ance. 10 0? 0.1f 0.1f 0.1f 0.1f 50k? 50k? clk? clk+ adc clock input clock input ad951x lvds driver 08678-020 fig ure 49 . differential lvds sample clock (up to 625 mhz) in some applications, it may be acceptable to drive the sample clock inputs with a single - ended 1.8 v cmos signal. in such applica tions, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f c a pacitor (see figure 50 ). optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? clock input ad951x cmos driver 08678-021 figure 50 . single - ended 1.8 v cmos input clock (up to 200 mhz)
data sheet ad9266 rev. a | page 21 of 32 input clock divider the ad9266 contains an input clock di vider with the ability to divide the input clock by integer values between 1 and 8. optimum performance can be obtained by enabling the internal duty cycle stabilizer (dcs) when using divide ratios other than 1, 2, or 4. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sens i tive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9266 c ontains a duty cycle stab i lizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance o f the ad9266 . noise and distortion perform - ance are nearly flat for a wide range of duty c y cles with the dcs on, as shown in figure 51. 80 79 78 77 76 70 71 72 73 74 75 30 35 40 45 50 55 60 65 70 snr (dbfs) positive duty cycle (%) dcs off dcs on 08678-064 figure 51 . snr vs. dcs on / off jitter in the rising edge of the in put is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz nominally. the loop has a time constant associated with it that must be considered in ap plications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop i s relocked to the input signal. jitter considerations high speed, high resolutio n adcs are sensitive to the quality of the clock input. the degradation in snr from the low frequency snr (snr lf ) at a given input frequency ( f input ) due to jitter ( t jrms ) can be calc u lated by snr hf = ?10 log[(2 f input t jrms ) 2 + 10 ) 10 / ( lf snr ? ] in the previous equation, the rms aperture jitter represents the clock input jitter specification. if undersampling applications are particularly sensitive to jitter, as illustrated in figure 52. 80 75 70 65 60 55 50 45 1 10 100 1k frequency (mhz) snr (dbfs) 0.5ps 0.2ps 0.05ps 1.0ps 1.5ps 2.0ps 2.5ps 3.0ps 08678-022 figure 52 . snr vs. input frequency and jitter the clock input should be treated as an analog signal when aperture jitter may affect the dynamic range of the ad9266 . to avoid modulating the clock signal with digital noise, keep p ower supplies for clock dri vers separate from the adc output driver supplies . low jitter, crystal - controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another met h od), it should be retimed by the original clock at the last step. for more information, s ee the an - 501 application note and the an - 756 application note available at www.analog.com .
ad9266 data sheet rev. a | page 22 of 32 power dissipation an d standby mode as shown in fig ure 53 , the analog core power dissipated by the ad9266 is prop ortional to its sample rate. t he digital power dissipation of the cmos outputs are determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvd d current (idrvdd) can be calculated a s idrvdd = v drvdd c load f clk n where n is the number of output bits (nine , in the case of the ad9266 ). this maximum current occurs when every output bit switches on every clock cycle, that is, a full - scale square wave at the nyquist frequency of f clk /2. in practice, the drvdd current is estab - lished by the average number of output bits switching, which is determined by the sample rate and the characte r istics of the analog input signal. reducing the capacitive loa d presented to the output drivers can minimize digital power co n sumption. the data in figure 53 was taken using the same operating conditions as those used for the typical performance characteristics , w ith a 5 pf load on each ou t put driver. 08678-067 45 55 65 75 85 95 105 1 15 10 20 30 40 50 60 70 80 analog core power (mw) clock r a te (msps) ad9266-80 ad9266-65 ad9266-40 ad9266-20 figure 53 . analog core power vs. clock rate in spi mode , t he ad9266 can be placed in power - down mode directly via the spi port , or by using th e programmable external mod e pin. in non - spi mod e , power - down is achieved by asser t - ing the pd wn pin high . in this state, the adc typically dissipates 500 w. d u r i n g p o w e r - down, the output drivers are placed in a high impedance state. asserting pdwn low (or the mode pin in s pi mode) returns the ad9266 t o its normal operating mo de. note that pdwn is re f erenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power - down mode and then must be recharged when r e turning to normal operation. as a result, wake - up time is related to the time spent in power - down mode, and shorter power - down cycles result in proportio n ally shorter wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are re quired. see the memory map section for more details. digital outputs the ad9266 output drivers can be configured to interface with 1.8 v to 3.3 v cmos logic families. o utput data can also be multiplexed onto a single output bus t o reduce the total number of traces required. the cmos output drivers are sized to provide suff i cient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies and may affect conv erter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. the output data format can be selected to be either offset binary or twos complement by setting the sclk/dfs pin w hen opera t ing in the external pin mode (see table 11). as detailed in the an - 877 application note, interfacing to high speed adcs via spi , the data format can be selected for offset binary, twos complement, or gray code when usin g the spi co n trol. table 11 . sclk/dfs and sdio/pdwn mode selection (external pin mode) voltage at pin sclk/dfs sdio/pdwn agnd offset binary (default) normal operation (default) drvdd twos complement outputs disabled digital outp ut enable function ( oeb ) when using the spi interface, the data outputs and dco can be independently three - stated by using the programmable external mode pin . the mode pin (oeb) function is enabled via bits[ 6:5 ] of register 0x 0 8 . if the mode pin is configu red to operate i n traditional oeb mode and the mode pin is low, the output data drivers and dcos are enabled. if the mode pin is high, the ou t put data drivers and dcos are placed in a high impedance state. this oeb function is not intended for rapid access to the data bus. note that the mode pin is re f erenced to the digital output driver supply (drvdd) and should not exceed that supply voltage.
data sheet ad9266 rev. a | page 23 of 32 timing the ad9266 provides latched data with a pipeline d e lay of eight clock cycles. data outputs are available o ne propagation d e lay (t pd ) after the rising edge of the clock signal. minimize t he length of the output data lines and loads placed on them to reduce transients within the ad9266 . these transients can degrade converter dynamic perfor m ance. the lowest typi cal conversion rate of the ad9266 is 3 msps. at clock rates below 3 msps, dynamic performance may d e grade. data clock output (dco) the ad9266 provides a data clock output (dco) signal that is intended for capturing the data in an external regi s ter. t he cm os data outputs are valid on the rising edge of dco, unless the dco clock polarity has been changed via the spi. see figure 2 for a graphical timing d e scription. table 12 . output data format input (v) con dition (v) offset binary output mode twos complement mode or vin+ ? vin? < ?vref ? 0.5 lsb 00 00 0000 0000 0000 1000 0000 0000 0000 1 vin+ ? vin? = ?vref 00 00 0000 0000 0000 1000 0000 0000 0000 0 vin+ ? vin? = 0 10 00 0000 0000 0000 00 00 0000 0000 0000 0 vin+ ? vin? = +vref ? 1.0 lsb 1111 1111 1111 1111 0111 1111 1111 1111 0 vin+ ? vin? > +vref ? 0.5 lsb 1111 1111 1111 1111 0111 1111 1111 1111 1
ad9266 data sheet rev. a | page 24 of 32 output test the ad9266 includes v arious output test options to place predictable v alues on the outputs of the ad9266 . output test modes the output test options are described in table 16 at address 0x0d. when an output test mode is enabled, the anal og section of the adc is discon nected from the digital back en d blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. th ese tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an - 877 application note, interfacing to high speed adcs via spi .
data sheet ad9266 rev. a | page 25 of 32 serial p ort i nt erface ( spi ) the ad9266 serial port interface (spi) allows the user to co n - figure the converter for specific funct ions or operations through a structured register space provided inside the adc . the spi gives the user added flexibility and customization, d epending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divi ded into fields, which are docu mented in the memory map section . f or more detailed oper a tional information, see the an - 877 a pplication note , interfacing to high speed adc s via spi . configuration using the spi three pins define the s pi of this adc: sclk , sdio , and csb (see table 13 ). the sclk (a serial clock) is used to sy n chronize the read and write data presented from and to the adc. sdio (serial data input/output) is a dual - purpose pin that allow s data to be sent and read from the internal adc memory map regi s ters. the csb (chip sel ect bar) is an active - low control that enables or di s ables the read and write cycles. table 13 . serial port interface pins pin function sclk serial clock . the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data input / output . a dual - purpose pin that typically serves as an input or an output, d e pending on the instruction being sent and the relative position in the timing frame. csb chip select bar . an active - low control that g ates the read and write cycles. the falling edge of csb , in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 54 and table 5 . other modes involving the csb pin are available. csb can be held low indefinitely, which permanently enables the device ; this is called streaming. csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by t he w0 and w1 bits , as sh own in figure 54 . all data is composed of 8 - bit words. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. this allows the serial data i n put/output (sdio ) pin to change direction from an input to an output at the appropriate point in the serial frame . in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowin g the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the serial data input/ output (sdio) pin to change direction from an input to an ou t put at the appropriate point in the serial frame. data can be sent in msb - first mode or in lsb - first mode. msb first is the default on power - up and can be changed via the spi port co n figuration register. for more information about this and other feature s, see the an - 877 application note , interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 08678-023 figure 54 . serial port interface timing diagra m
ad9266 data sheet rev. a | page 26 of 32 hardware interface the pins described in table 13 constitute the physical i nterface between the programming d e vice of the user and the serial port of the ad9266 . the sclk pin and the csb pin function as inp uts when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , micro - controller - based serial port interface (spi) boot ci rcuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9266 to prevent these signals from transi - tioning at the converter inputs during critical sampling periods. sdio/pdwn and sclk/dfs serv e a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power - on, they are associated with a specific function. the digital outputs section describes the strappable functions su p ported on the ad9266 . configuration withou t the spi in applications that do not interface to the spi control registers, the sdio/pdwn pin and the sclk/dfs pin serve as standalone cmos - co m patible control pins. when th e device is powered up, it is assumed that the user intends to use the pins as static control lines for the power - down and output data format feature control. in this mode, connect the csb chip select to drvdd, which di s ables the serial port interface. tab le 14 . mode selection pin external voltage configuration sdio/pdwn drvdd chip power - down mode agnd (default) normal operation (default) sclk/dfs drvdd twos compl e ment enabled agnd (default) offset binary enabled spi accessib le features table 15 provides a brief description of the general features that are accessible via the spi. these features are d e scribed in detail in the an - 877 application note , interfacing to high speed adcs via spi . the ad9266 p art - specific features are described in detail in table 16 . table 15 . features accessible using the spi feature description mode s allows the user to set either power - down mode or standby mode clock allow s the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay
data sheet ad9266 rev. a | page 27 of 32 memory map reading the memory m ap register table each row in the memory map register table (see table 16) contains eight bit locations. the memory map is roughly divided into four sections: the chip co n figuration registers (address 0x00 to address 0x02); the device index and transfer register (address 0xff); the program registers, including setup, control, and test (address 0x08 to addres s 0x2a); and the ad9266 - specific customer spi control register (address 0x101). table 16 documents the default hexadecimal value for each hexa - decimal a d dress shown. the column with the heading bit 7 (msb) is the start of the def ault hexadecimal value given. for example, address 0x2a, the or/mode select register, has a hexa decimal default value of 0x01. this means that in address 0x2a, bits[7:1] = 0, and bit 0 = 1. this setting is the default or/mode setting. the default value res ults in the programmable external mode/or pin (pin 23) functioning as an out - of - range digital output. for more information on this function and others, see the an - 877 application note, interfacing to high speed adcs via spi. this application note details t he functions controlled by register 0x00 to register 0xff. the remaining register, register 0x101, is docu mented in the memory map register descriptions section that follows table 16. open locations all a ddress and bit locations that are not included in the spi map are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these loca - tions is required only when part of an address location is o pen (for example, address 0x2a). if the entire address location is open, it is omitted from the spi map (for e x ample, address 0x13) and should not be written. default values after the ad9266 is reset, critical registers are loaded with default values. the default values for the regi s ters are given in the memory map register table (see tabl e 16) . logic levels an explanation of logic level terminology follows: ? bit is set is sy n onymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x08 to address 0x18 are shadowed. writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simulta - neously when the transfer bit is set. the internal update takes place when the transfer bit is set, and then the bit autoclea rs.
ad9266 data sheet rev. a | page 28 of 32 memory map register table all address and bit locations that are not included in table 16 are not currently supported for this device. table 16. addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments chip configuration registers 0x00 spi port configuration 0 lsb f irst soft r eset 1 1 soft r eset lsb f irst 0 0x18 the nibbles are mirrored so that lsb - or msb - first mode register s corr ectly, r ega rdless of shift mode . 0x01 chip id 8 - bit chip id , bits [ 7:0 ] ad9266 = 0x 7 8 read only unique chip id used to differentiate devices; r ead only . 0x02 chip grade open speed g rade id , bits [ 6:4 ] (identify device variants of c hip id) 20 msps = 000 40 msps = 001 65 msps = 010 80 msps = 011 open read only unique speed grade id used to differentiate devices; r ead only . dev ice index and transfer register 0xff transfer open transfer 0x00 synchronously transfers data from the master shift register to the slave . prog ram registers 0x08 modes external pin 23 mode input enable external pin 23 function when high 00 = full power - down 01 = standby 10 = normal mode: output disabled 11 = normal mode: output enabled open 00 = chip run 01 = full power - down 10 = standby 11 = ch ip wide digital reset 0x00 determines various generic modes of chip operation . 0x09 clock open duty cycle stabilize 0x01 enable internal duty cycle stabilizer (dcs) . 0x0b clock divide open clock divider , bits [ 2:0 ] clock divide ratio : 000 = divide by 1 00 1 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 the divide ratio is the value plus 1 . 0x0d test mode user test mode 00 = single 01 = alternate 10 = single once 11 = alternate once reset pn long gen reset pn short gen output test mode , bits [ 3:0 ] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = 1 / 0 word toggle 1000 = user input 1001 = 1 / 0 bit toggle 1010 = 1 sync 1011 = one bit high 1100 = m ixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data . 0x10 offset adjust 8 - bit device offset adjustment , bit s [ 7:0 ] (local) offset adjust in lsbs from +127 to ? 128 (twos complement format) 0x00 device offset trim . 0x14 output mode 00 = 3.3 v cmos 10 = 1.8 v cmos open output disable open output invert 00 = offset binary 01 = two s complement 10 = gray code 11 = o ffset binary 0x00 configures the out puts and the format of the data .
data sheet ad9266 rev. a | page 29 of 32 addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def ault value (hex) comments 0x15 output a djust 3.3 v dco drive strength 00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes 1.8 v dco drive strength 00 = 1 stripe 01 = 2 stripes 10 = 3 stripes (de fault) 11 = 4 stripes 3.3 v data drive strength 00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes 1.8 v data drive strength 00 = 1 stripe 01 = 2 stripes 10 = 3 stripes (default) 11 = 4 stripes 0x22 determines cmos o utput drive strength properties . 0x16 output phase dco o utput polarity 0 = normal 1 = inverted open in put clock phase adjust, bits[2:0] (value is number of inp ut clock cycles of phase delay) 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clo ck cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles 0x00 on devices that use global clock divide, determines which phase of the divider output is used to supply the output clock; internal la tching is unaffected . 0x17 output delay enable dco delay open enable d ata delay open dco / data delay [ 2:0 ] (typical values) 000 = 0.56 n s 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns 0x00 sets the fine ou tput delay of the output clock but does not change internal timing . ( t ypical values) 0x19 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user - d efined pattern, 1 lsb . 0x1a user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user - d efined pattern, 1 msb . 0x1b u ser_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 0x00 user - d efined pattern, 2 lsb . 0x1c user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 0x00 user - d efined pattern, 2 msb . 0x2a or/mode select open 0 = mode 1 = or (default) 0x01 selects i/o functionality in conjunction w ith addr ess 0x08 for mode (input) or or (output) on e xternal pin 23 . ad9266 - specific customer spi control register 0x10 1 usr2 open enable gclk detect run gclk open disable sdio pull - down 0x08 enables internal oscillator for clock rates of <5 mhz .
ad9266 data sheet rev. a | page 30 of 32 memo ry map register desc riptions for additional information about functions that are controlled in register 0x00 to register 0xff, see the an - 877 application note, interfacing to high speed adcs via spi at www.analog.com . usr2 (register 0x101) bit enable gcl detect normally set high , this bit enables a circuit that detects e ncode rates below about 5 msps . when a low encode rate is detected , an internal oscillator, gclk , is enabled , ensuring the proper operation of sev eral circuits. if set low , the detector is disabled. bit 2 run gclk this bi t enables the gclk oscillator. for some applications with encode rates below 10 msps , it may be preferable to set this bit high to supersede the gclk detector. bit 0 disable sdio pu ll - down this bit can be set high to disable the internal 30 k pull - down on the sdio pin , which ca n be used to limit the loading when many devices are connected to the spi bus.
data sheet ad9266 rev. a | page 31 of 32 applications informa tion design guidelines before starting design and layout of the ad9266 as a system, it is recommended that the design er become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad9266 , it is strongly recom - mended that two separate sup plies be used. use one 1.8 v supply for analog (avdd); use a separate 1.8 v to 3.3 v supply for the digital output supply (drvdd). if a common 1.8 v avdd and drvdd supply must be used, the avdd and drvdd domains must be isolated with a ferrite bead or filt er choke and separate decoupling capacitors. several different decoupling capacitors can be used to cover both high and low frequencies. locate t hese capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal tr ace length. a single pcb ground plane should be sufficient when using the ad9266 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum perform ance is easily achieved. exposed paddle thermal heat sink recomme ndations the exposed paddle (pin 0) is the only ground connection for the ad9266 ; therefore , it must be connected to analog ground (agnd) on the customers pcb. to achieve the best electrical and thermal performance, mate an exposed (no solder mask) contin uous copper plane on the pcb to the ad9266 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. fill or plug these vias with nonc onductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, a silkscreen should be overlaid to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb du ring the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. for detailed information about packaging and pcb layout of chip scale packages, see the an - 772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) at www.analog.com . encode clock for optimum dynamic performance , a low jitter encode clock source with a 50% duty cycle 5% should be used to clock th e ad9266 . vcm the vcm pin should be decoupled to ground with a 0.1 f c a pacitor, as shown in figure 38 . rbias the ad9266 requires that a 10 k? resistor be placed between the rbias pin and ground. this resistor sets the master current reference of the adc core and should have at least a 1% to l erance. reference decoupling e xternally decouple the vref pin to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active dur ing periods when the full dynamic performance of the converter is required. because the sclk, csb , and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9266 to keep these signals from transitioning at the converter inputs during critical sampling periods.
ad9266 data sheet rev. a | page 32 of 32 outline dimensions 08-16- 2010-b 1 0.50 bsc b o t t o m v i e w t o p v i e w pin 1 indic a t or 3 2 9 1 6 1 7 2 4 2 5 8 e x p o s e d p a d pin 1 indica t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for prope r conne ction of the exposed pad, refer to the pin configuration and funct ion descr ipti ons section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * complian t to jedec standards mo-220-whh d-5 with exception to exposed pad dimension. figure 55 . 32 - lead l ead f rame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp - 32 - 12 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9266 bcpz -80 C 40c to +85c 32- lead lead f rame chip scal e package (lfcsp_w q) cp -32-12 ad9266 bcpzrl7 -80 C 40c to +85c 32- lead lead f rame chip scale package (lfcsp_w q) cp -32-12 ad9266 bcpz -65 C 40c to +85c 32- lead lead f rame chip scale package (lfcsp_w q) cp -32-12 ad9266 bcpzrl7 -65 C 40c to +85c 32- lead lead f rame chip scale package (lfcsp_w q) cp -32-12 ad9266 bcpz - 40 C 40c to +85c 32 - lead lead f rame chip scale package (lfcsp_w q) cp - 32 - 12 ad9266 bcpzrl7 -40 C 40c to +85c 32- lead lead f rame chip scale package (lfcsp_w q) cp -32-12 ad9266 bcpz -20 C 40c to +85c 32- lead lead f rame chip scale package (lfcsp_w q) cp -32-12 ad9266 bcpzrl7 -20 C 40c to +85c 32- lead lead f rame chip scale package (lfcsp_w q) cp -32-12 ad9266 - 80ebz evaluation board ad9266 - 65ebz evaluation board ad9266 - 40ebz evaluation board ad92 66- 20ebz evaluation board 1 z = rohs compliant part. ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08678 - 0- 6/12(a)

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